Quantum Well FET(QWFET)

Quantum mechanical effects become important when device geometries are scaled down to nanometer range. In ultra deep submicron regime, quantum mechanical effects can be a show stopper for device integration. InSb QWFET is a device utilizing the high mobility of InSb. InSb QWFET based circuits will consume less power and ultra high switching speeds can be achieved using it.
The quantum well transistor architecture employs barrier layers with higher band-gap materials to mitigate the effect of the narrow band-gap InSb on device leakage and breakdown.The transistors were fabricated on a semi-insulating GaAs substrate using a relaxed metamorphic buffer layer of AlyIn1-ySb to accommodate lattice mismatch, a compressively strained InSb quantum well confined between layers of AlxIn1-xSb and a Schottky barrier metal gate. High speed carrier transport occurs in the low band-gap InSb quantum well (QW). The buffer layer is made of AlkIn1-kSb, with the indium concentration graded so that it can match the lattice constant of both the GaAs substrate and the InSb channel.

The high speed of operation is achieved using the material property of InSb as well as the property of quantum wells.InSb is known to be the greatest mobility semiconductor. A remote doping concept is used to get ride of the impurity scattering.An extractive technology (substrate bias with potential hill)is used to extract the thermally generated carriers so that the device can be operated at room temp.

For high speed direct coupled FET logic (DCFL) applications, both enhancement (i.e. positive VT) and depletion mode devices are required. An enhancement mode InSb QWFET is demonstrated for the first time using a deep recess etch in the gate region, which shows a peak fT of 305GHz at 0.5V VDS. A depletion mode device is demonstrated at the same time utilizing a shallow recess gate with a peak fT of 256GHz at 0.5V VDS. The demonstration of both high performance depletion and enhancement mode InSb QWFETs makes the technology a promising candidate for future high speed, low power logic applications. Enhancement device achieve record intrinsic speed of 305GHz .The record speed of the enhancement device is due to the deep recess etch. The deep recess etch increases the gate control of the device as described by the MOSFET ID(sat) equation. Recessed gate architecture improves the gate field to quantum well coupling, improving scalability. Scalability further increases by buffer p-type doping.

Learning VerilogHDL

There are several ways of representing digital logic.One method employed to simplify the complexity in transfering the schematic representations is to use HDLs(hardware description languages).One popular one is Verilog HDL. Although there are no packages and libraries available in Verilog ,its simpler because of its similarity in format compared to C language.Note that the C is a sequntial laguage running on sequential device ,while the Verilog is a HDL which is only for the hardware! its not a programming language!
Another great thing about this Verilog is that it allows various levels of abstraction
We can have a structural style a data flow style or a behavioural style!The Verilog HDL is an event driven one.(assuming fedora, am in fedora9)We require a open source tools such as cver and gtk wave for simulation and result.gtk wave is a waveform viewer.There are many more tools available.
The basic functional block in Verilog is the "module"
A typical module statement may look like module halfadder(A,B,S,Cout);
where the A,B,S,Cout are the input and output list of a half adder





The code for generating a half adder is shown
(open any editor,vim ,gedit ,any edit type the following code)
module halfadder(A,B,S,Cout);
input A,B;
output S,Cout;
xor x1(S,A,B);//since this is a primitive we cannot specify the portlist as we wish
//the format is output followed by input
and a1(Cout,A,B);
endmodule
we save this as a file (say) ha.v
The above specified code is a structural description of half adder.after creating this we have created a half adder in verilog. This can be given to the synthesis tool.For varification of the logic of the ckt we need testbenches to be written .

`timescale 1ns/1ps
`include "ha.v"
module ha_tb;
reg A_t,B_t;
wire S_t,Cout_t;

halfadder UUT(.A(A_t),.B(B_t),.S(S_t),.Cout(Cout_t));
initial
begin
$dumpfile("ha.vcd");
$dumpvars(2,ha_tb.UUT);
end

initial
begin
A_t=1'b0;
B_t=1'b0;
#5 A_t=~A_t;
#5 B_t=~B_t;
#5 A_t=~A_t;
end
initial
#30 $finish;
endmodule


after saving this in another name ha_tb.v,we can simulate the half adder with the help of test bench and cver writing
user$]cver ha_tb.v to the terminal .Then it will generate a value change dump file called ha.vcd in the same directory which can be opened through GTKwave for viewing the simulation result!