Saturday, August 9, 2008



Fig. 1. The racetrack is a ferromagnetic nanowire, with data encoded as a pattern of magnetic domains along a portion of the wire. Pulses of highly spin-polarized current move the entire pattern of DWs coherently along the length of the wire past read and write elements. The nanowire is approximately twice as long as the stored DW pattern, so the DWs may be moved in either direction. (A) A vertical-configuration racetrack offers the highest storage density by storing the pattern in a U-shaped nanowire normal to the plane of the substrate. The two figures show the magnetic patterns in the racetrack before and after the DWs have moved down one branch of the U. past the read and write ele­ments, and then up the other branch. (B) A horizontal config­uration uses a nanowire parallel to the plane of the substrate. (C)Reading data from the stored pattern is done by measuring the tunnel magnetoresistance of a magnetic tunnel junction element connected to the racetrack. (D) Writing data is accomplished, for example, by the fringing fields of a DW moved in a second ferromagnetic nanowire oriented at right angles to the storage nanowire. (E) Arrays of racetracks are built on a chip to enable high-density storage.

RM is fundamentally a shift register in which the data bits (the DWs) are moved to and fro along any given racetrack to intersect with individual reading and writing elements integrated with each racetrack.Permalloy is the term for a nickel iron magnetic alloy. Generically, it refers to an alloy with about 20% iron and 80% nickel content. Permalloy has a high magnetic permeability, low coercivity, near zero magnetostriction, and significant anisotropic magnetoresistance.

Advantages of racetrack memory over the other types of memory

Alternative for HDDs and existing solid state memories except SRAM.

100 times bits/area than SRAM

Greater operating speed and less power consumption

Can be 3D.

can replace the current architecture of memory in computers

Friday, August 1, 2008


High K Metal Gate Technology (HKMG)

Dielectric leakage problem

Dielectric leakage is problem faced during scaling the MOSFET
This happens because of the tunneling of the electrons through the thin dielectric
As the width(physical) of the dielectric reduces leakage becomes more due to tunneling

High K Solution

The problem however can be overcome by the usage of High K dielectric.This shows that the ,material must be electrically thin but physically thick(Hafnium oxide ).For the same capacitance the oxide thickness of the high K dielectric (oxide) can be more .

Problem with the polysilicon gate
  • Polysilicon depletion
  • Need for enhanced channel mobility

Potential solution

No depletion, very low resistance gate, no boron penetration, compatibility with high-k
Also lesser phonon scattering, hence enhanced mobility