Quantum mechanical effects become important when device geometries are scaled down to nanometer range. In ultra deep submicron regime, quantum mechanical effects can be a show stopper for device integration. InSb QWFET is a device utilizing the high mobility of InSb. InSb QWFET based circuits will consume less power and ultra high switching speeds can be achieved using it.
The quantum well transistor architecture employs barrier layers with higher band-gap materials to mitigate the effect of the narrow band-gap InSb on device leakage and breakdown.The transistors were fabricated on a semi-insulating GaAs substrate using a relaxed metamorphic buffer layer of AlyIn1-ySb to accommodate lattice mismatch, a compressively strained InSb quantum well confined between layers of AlxIn1-xSb and a Schottky barrier metal gate. High speed carrier transport occurs in the low band-gap InSb quantum well (QW). The buffer layer is made of AlkIn1-kSb, with the indium concentration graded so that it can match the lattice constant of both the GaAs substrate and the InSb channel.
The high speed of operation is achieved using the material property of InSb as well as the property of quantum wells.InSb is known to be the greatest mobility semiconductor. A remote doping concept is used to get ride of the impurity scattering.An extractive technology (substrate bias with potential hill)is used to extract the thermally generated carriers so that the device can be operated at room temp.
For high speed direct coupled FET logic (DCFL) applications, both enhancement (i.e. positive VT) and depletion mode devices are required. An enhancement mode InSb QWFET is demonstrated for the first time using a deep recess etch in the gate region, which shows a peak fT of 305GHz at 0.5V VDS. A depletion mode device is demonstrated at the same time utilizing a shallow recess gate with a peak fT of 256GHz at 0.5V VDS. The demonstration of both high performance depletion and enhancement mode InSb QWFETs makes the technology a promising candidate for future high speed, low power logic applications. Enhancement device achieve record intrinsic speed of 305GHz .The record speed of the enhancement device is due to the deep recess etch. The deep recess etch increases the gate control of the device as described by the MOSFET ID(sat) equation. Recessed gate architecture improves the gate field to quantum well coupling, improving scalability. Scalability further increases by buffer p-type doping.
The quantum well transistor architecture employs barrier layers with higher band-gap materials to mitigate the effect of the narrow band-gap InSb on device leakage and breakdown.The transistors were fabricated on a semi-insulating GaAs substrate using a relaxed metamorphic buffer layer of AlyIn1-ySb to accommodate lattice mismatch, a compressively strained InSb quantum well confined between layers of AlxIn1-xSb and a Schottky barrier metal gate. High speed carrier transport occurs in the low band-gap InSb quantum well (QW). The buffer layer is made of AlkIn1-kSb, with the indium concentration graded so that it can match the lattice constant of both the GaAs substrate and the InSb channel.
The high speed of operation is achieved using the material property of InSb as well as the property of quantum wells.InSb is known to be the greatest mobility semiconductor. A remote doping concept is used to get ride of the impurity scattering.An extractive technology (substrate bias with potential hill)is used to extract the thermally generated carriers so that the device can be operated at room temp.
For high speed direct coupled FET logic (DCFL) applications, both enhancement (i.e. positive VT) and depletion mode devices are required. An enhancement mode InSb QWFET is demonstrated for the first time using a deep recess etch in the gate region, which shows a peak fT of 305GHz at 0.5V VDS. A depletion mode device is demonstrated at the same time utilizing a shallow recess gate with a peak fT of 256GHz at 0.5V VDS. The demonstration of both high performance depletion and enhancement mode InSb QWFETs makes the technology a promising candidate for future high speed, low power logic applications. Enhancement device achieve record intrinsic speed of 305GHz .The record speed of the enhancement device is due to the deep recess etch. The deep recess etch increases the gate control of the device as described by the MOSFET ID(sat) equation. Recessed gate architecture improves the gate field to quantum well coupling, improving scalability. Scalability further increases by buffer p-type doping.
