There are several ways of representing digital logic.One method employed to simplify the complexity in transfering the schematic representations is to use HDLs(hardware description languages).One popular one is Verilog HDL. Although there are no packages and libraries available in Verilog ,its simpler because of its similarity in format compared to C language.Note that the C is a sequntial laguage running on sequential device ,while the Verilog is a HDL which is only for the hardware! its not a programming language!
Another great thing about this Verilog is that it allows various levels of abstraction
We can have a structural style a data flow style or a behavioural style!The Verilog HDL is an event driven one.(assuming fedora, am in fedora9)We require a open source tools such as cver and gtk wave for simulation and result.gtk wave is a waveform viewer.There are many more tools available.
The basic functional block in Verilog is the "module"
A typical module statement may look like module halfadder(A,B,S,Cout);
where the A,B,S,Cout are the input and output list of a half adder
The code for generating a half adder is shown
(open any editor,vim ,gedit ,any edit type the following code)
module halfadder(A,B,S,Cout);
input A,B;
output S,Cout;
xor x1(S,A,B);//since this is a primitive we cannot specify the portlist as we wish
//the format is output followed by input
and a1(Cout,A,B);
endmodule
we save this as a file (say) ha.v
The above specified code is a structural description of half adder.after creating this we have created a half adder in verilog. This can be given to the synthesis tool.For varification of the logic of the ckt we need testbenches to be written .
`timescale 1ns/1ps
`include "ha.v"
module ha_tb;
reg A_t,B_t;
wire S_t,Cout_t;
halfadder UUT(.A(A_t),.B(B_t),.S(S_t),.Cout(Cout_t));
initial
begin
$dumpfile("ha.vcd");
$dumpvars(2,ha_tb.UUT);
end
initial
begin
A_t=1'b0;
B_t=1'b0;
#5 A_t=~A_t;
#5 B_t=~B_t;
#5 A_t=~A_t;
end
initial
#30 $finish;
endmodule
after saving this in another name ha_tb.v,we can simulate the half adder with the help of test bench and cver writing
user$]cver ha_tb.v to the terminal .Then it will generate a value change dump file called ha.vcd in the same directory which can be opened through GTKwave for viewing the simulation result!
Another great thing about this Verilog is that it allows various levels of abstraction
We can have a structural style a data flow style or a behavioural style!The Verilog HDL is an event driven one.(assuming fedora, am in fedora9)We require a open source tools such as cver and gtk wave for simulation and result.gtk wave is a waveform viewer.There are many more tools available.
The basic functional block in Verilog is the "module"
A typical module statement may look like module halfadder(A,B,S,Cout);
where the A,B,S,Cout are the input and output list of a half adder
The code for generating a half adder is shown
(open any editor,vim ,gedit ,any edit type the following code)
module halfadder(A,B,S,Cout);
input A,B;
output S,Cout;
xor x1(S,A,B);//since this is a primitive we cannot specify the portlist as we wish
//the format is output followed by input
and a1(Cout,A,B);
endmodule
we save this as a file (say) ha.v
The above specified code is a structural description of half adder.after creating this we have created a half adder in verilog. This can be given to the synthesis tool.For varification of the logic of the ckt we need testbenches to be written .
`timescale 1ns/1ps
`include "ha.v"
module ha_tb;
reg A_t,B_t;
wire S_t,Cout_t;
halfadder UUT(.A(A_t),.B(B_t),.S(S_t),.Cout(Cout_t));
initial
begin
$dumpfile("ha.vcd");
$dumpvars(2,ha_tb.UUT);
end
initial
begin
A_t=1'b0;
B_t=1'b0;
#5 A_t=~A_t;
#5 B_t=~B_t;
#5 A_t=~A_t;
end
initial
#30 $finish;
endmodule
after saving this in another name ha_tb.v,we can simulate the half adder with the help of test bench and cver writing
user$]cver ha_tb.v to the terminal .Then it will generate a value change dump file called ha.vcd in the same directory which can be opened through GTKwave for viewing the simulation result!
